OTHER-1 Instruction Set Details
The memory reference instructions have a 10 bit address field and 2 control bits that determine the addressing mode: absolute in the current 1024 word page or relative to the current location, a direct address or and indirect reference or memory increment (for ISV, ISA instructions). An indirectly referenced location has a similar address format that can continue or terminate the indirect referencing.
Stand-alone address words indirectly referenced by an instruction also have two control bits to specify possible further indirection and absolute or relative type: relative is again a 10 bit field, but absolute is a 12 bit field allowing addressing of the full 4K words of implemented core memory. See Memory Reference Instructions and Addressing Mode Descriptions page for further detail.
The I/O instruction works with the A accumulator and a 16 bit parallel data I/O bus. A accumulator data is available to the I/O device during the first part of the I/O time, and device data can be loaded into the A accumulator during a later part of the I/O time. 16 devices can be addressed, and controlled with a 3-bit function code - typically set/clear states, test and skip if done, etc.
The Miscellaneous instruction implements loading the control panel toggle switch settings (the Switch Register) into the A register, enable/disable interrupts, and the Halt operation. (Actual I/O interrupt functionality was never implemented in the OTHER-1.)