CPU Logic

Last update: 8/27-30/2020 - Added a CPU Data Path block diagram, data path overview, I & E cycle
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CPU Logic Drawings

About the Drawings

Photographs of the original OTHER-1 logic drawings related to the implementation of the Central Processing Unit (CPU) are presented here. The drawings were done with pencil on tracing paper with orange grid lines Though most had the grid on the reverse side, black and white copies were still hard to read, so the photos help a lot.

Usually a drawing was done following the implementation using design sketches and prepared wiring lists and limited static testing with power applied. A Xerox of the drawing was made, and any subsequent red-line changes were made to the copy and the wiring lists, but not to the original tracing.

Signals with off-page connections are consistently and uniquely named, and reference drawing numbers are usually provided with the name. A complete listing of such connections was maintained in a set of named-signal wiring lists, not provided here.

Reading and Navigating the Drawings

All of the OTHER-1 logic circuit drawings and physical board layouts which have been uploaded to this site are located in the Photo Gallery as albums:
- Core Memory Logic
- Other-1 Board Layouts

- CPU Logic

All of the CPU logic circuit drawings appear on this page. There are about 50 CPU and Memory logic circuit drawings in all for the OTHER-1, some multi-sheet, and others extra wide.

The Board Layouts are wiring-side views of the of the physical locations of the integrated circuits (ICs) used in the computer's construction. Most of the ICs are small scale digital TTL circuits, 14 or 16 pin, and are plugged into wire-wrap sockets mounted on pre-drilled phenolic boards. The Board Layouts are marked with a coordinate system - numbers 1 to 25 across the top and letters across the left side - the letters are unique for the four large 6" x 17" circuit boards:
- A, B, C, D, E  --Instruction Control Logic Board - CPU   (drawings 13 - 31)
- F, G, H, J, K  -- Registers Board - CPU   (drawings 01 - 12)
- L, M, N, P, S -- X-Y Drivers Board - Memory
- T, U, V, X, Y, Z  -- Inhibit Drivers Board - Memory

On the CPU board drawings, each rectangle depicting an IC location is marked the IC type (e.g. 74155), and typically the number of pins (14, 16, 24), and unused logic gates in the IC (usually 0). Along the bottom, the general purpose of each group of ICs is indicated, and loosely relates to the name of the associated Logic diagram.

See IC Reference page for links to IC datasheets.
On a typical Logic Circuit Drawing, each used logic component is separately depicted, regardless of of how many such components are in the same IC package. The symbols used for the logic components are usually those appearing in the IC maker's handbook or data sheets (typically Texas Instruments).

Off-diagram connections are labelled: the label name indicates the True or Active sense of the signal: an over-score on the name indicates the signal is True or Active when logical "0" or "low" (0 volts) - called "active low"; lack of the over-score indicates True or Active when logical "1" or "high" (3 volts) - called "active high".

The drawings on this page indicate an "active low" signal name with an overscore, while text on this page will indicate an active low signal name with  "(low)" appearing before the name.

Typical CPU Logic drawing (28 Reset / Iin), showing labeling:
- drawing number (used for off-page references) and title
- off-page references (e.g., drawing # 19 and 26 for signal "Iin")
- true when high (e.g. "reset") and true when low (e.g. over-scored "sys reset A") signals
- common gate depiction (e.g. "and" gates)
- marking of board coordinates and pin-out of each logic element (e.g., gates at 20D)
- separate depiction of individual logic elements in same package (e.g. 2 gates at 20D)
- special markings (e.g., gate with Schmitt-trigger inputs at coordinate 21A)
Each logic component symbol will contain a number+character label inside (e.g., "5T") indicating the coordinates of it's containing IC on a Board Layout. (Other notations inside the symbol are generally those of the IC maker. I have marked some logic symbols "OC" to indicate an open-collector output.) Around the outside of the symbol, at the wiring connection points, are the IC pin numbers used for this logic component. Several logic components sharing the same IC package will have the same IC coordinates label, but will have different pin numbers. Connections across a multi-sheet drawing are labelled and the connections drawn with arrows: "-->" or ">--".
CPU Architecture Overview
CPU Data Path

16 bits wide: busses and logic.

The A buss is fed by program data output of A register, and the B buss by the B register; these are inputs to the arithmetic logic unit, which combines them into a 16 bit output, followed by a shift register. The shift register output feeds the C buss, which provides input to the A and/or B registers.

The A and/or B busses are also fed by outputs of these CPU registers:
 Instruction Counter  (to B),
 Instruction Register (to A),
 Address Register (14 bits to B),
 Memory Data Register (to both A and B),
 Switch Register (to B),
and the C buss feeds the inputs of all these registers, except the Instruction Register fed by B, and the Switch Register, fed by the Panel Toggle Switches.

Registers in Devices on the I/O buss are fed by the A register, and are inputs to the A register.
Instruction Types

All instructions are 16-bits (1 word) fixed length, and start on word boundaries. They are executed sequentially, except as altered by jump or skip instruction execution.
Memory Reference Instructions:
14 total, as determined by bits 2-5 of the instruction having values in range 0000 - 1101 binary. Bits 0, 1 determine the addressing mode of the instruction, while bits 6-15 contain the address value used to determine the initial address reference based on the mode.

I/O Instruction:
1 total, where bits 2-5 of the instruction have the value 1111 binary (and bits 0, 1 not used). Bits 8-15 control device selection, whether or not the A register is loaded from I/O data buss, and device-specific function

Operate Instructions:
4 total, where bits 2-5 of the instruction have the value 1110 binary, and bits 0, 1 determine the type:

- 00 - Combine:  Bits 6-15 control ALU function and arithmetic or logic mode, link usage, destination register (A, B)

- 01 - Shift:  Bits 6-15 control shift count, direction, link usage, shift or rotate, destination register (A, B)

- 10 - Test:  Bits 6-15 control test of any or all sign, overflow, zero, link. Skip next instruction or not based on result

- 11 - Miscellaneous:  Bits 6-9 control: load switch register, halt CPU (interrupt enable/disable reserved but not implemented)

Memory References

5 memory reference types, determined by bits 0 ("rel"), and 1 ("ind") of Memory Reference instructions or indirectly referenced locations (each containing their own "rel" and "ind" bits). These bits determine how the address value contained in the instruction word or the referenced location are to be used in calculating a final or continuing indirect reference.
- 00 - Absolute Direct
- 01 - Relative Direct
- 10 - Absolute Indirect
- 11 - Relative Indirect (instruction)
- 11 - Relative Increment (indirectly referenced location)

The 10 bits (bits 6-15) of address value in Memory Reference instructions is sufficient to address memory locations in the 1024 word page containing the instruction for Absolute references, or -512 to +511 locations relative to the instruction's address for Relative references.

A memory location can be indirectly referenced by a Memory Reference instruction or by another memory location so referenced. 12 bits (bits 4-15) of address value in such a location are used to address the full 4096 words of memory if the location's reference type is absolute ("rel" = 0); 10 bits (bits 6-15) are used to address a range -512 to +511 locations relative to the location's address if the type is relative ("rel" = 1). If the indirectly referenced memory location has both bits "rel" = 1 and "ind" = 1, the indirect chain is not continued; instead the location's address field is incremented, and the 10 bits used as the signed offset to a final address relative to the location's address.

Instruction Cycles  (BEING REVISED)

Instruction Fetch (I cycle): get the instruction at the address in the Instruction Counter (IC) from memory into the Instruction Register (IR).
A fixed number of clock cycles taken, including one read/write-refresh cycle of core-memory. An I cycle can be stretched if a core-memory instruction reference and possible chain of indirect references (further memory references) is involved.

Execute Instruction (E cycles): The instruction execution phase consists of 1 to 13 Execute (E) cycles (nominally a clock cycle each), each E cycle typically controlling movement of data from a source register through the CPU data bus, possibly modified at the ALU or shift register, and into a destination register. An E cycle can be stretched if a core-memory instruction reference and possible chain of indirect references (further memory references) is involved. At least one IC increment is always included as part of instruction execution (at the first E cycle - E1).
Data Path Registers


Each data path register (MDR, AR, IC, IR, A, B, and SW) has its own output control signals for putting its stored parallel content onto the A or B data buss via open-collector gates. The control signals are managed so that only one register has its output on any A or B buss at a given time. Each data path register (except the Switch Register which consists of manually set toggle switches) contains of a set of latches for storing parallel data content, and its own control signals for latching the parallel content from the C data buss. Similarly, I/O Devices interface directly with the A Register over the I/O buss via open-collector gated buffer registers, managed by I/O control logic for Device commands, status, and two-way data transfers. The "Wired-OR" of each bit line in a buss connecting open-collector gate outputs of multiple registers is maintained at a high voltage (~ 3-5 volts) by a pull-up resistor unless set low by an activated gate output.

On the A, B, and I/O busses a logical "1" is represented by a low voltage (~ 0 volts) and a logical 0 by a high voltage (~ 3-5 volts), while on the C data buss a logical 1 is represented by a high voltage and a logical 0 by a low voltage.

The Shift/Rotate Reg is the only register with output to the C buss; its output is available at all times.

For all instructions using A or B registers, except the Operate-Shift instruction, and all CPU supporting arithmetic, the Shift Register simply latches the output of the ALU and passes it on tho the C buss. For the Operate-Shift instruction, A Register or B Register data presented by the ALU is latched into the Shift Register, shifted/rotated per instruction, and passed on to the C buss.
Data Path Registers Details
01 Address Register: The Address Register (AR) is the interface buffer for addresses, specified by the CPU,  of data to be read or written by the core memory. See page Magnetic Core Memory Logic Details for additional information.

CHANGE: I had redlined copy of this drawing to add 2 latches (at 3K) and buffers (at 4K) to handle input bits C2, C3, and output bits B2, B3, using existing control signal "AR IN(4-5)" at gate output 1F4.

02 Memory Data Register: The Memory Data Register (MDR) is the interface buffer for data moving between the CPU and core memory. See page Magnetic Core Memory Logic Details for additional information.
03 Switch Register: The Switch Register (SW) is a set of 16 toggle switches located on the Other-1 front panel, settable by the operator. Outputs can be presented to the B buss. The switch settings are program readable via the Operate Miscellaneous instruction (drawing 20).

When the CPU is in manual mode, the SW is read by the deposit (DEP) push-button function to obtain the data to be written to memory, and by the load address (ADD) push-button function to obtain the start address for the DEP or EXAM push-button functions (drawing 27).
05 A Register, and 06 B Register: There are 10 memory reference and two Operate instructions that load, store, and manipulate data in the A and B general purpose registers. Output from these registers can be presented to the busses of the same name. The Operate Combine instruction is specifically purposed to provide the full range 72181 ALU function outputs using the A and B as input operands.

07 Instruction Counter: The Instruction Counter (IC) is not a hardware counter, but just a set of latches - when needed, it is incremented through the ALU. The IC is output to the B buss and loaded via the C buss. The IC is incremented in the first E cycle of every instruction. The instructions which can skip the next instruction (ISV, ISA, Operate Test, and I/O) will also increment the IC in a later E cycle if they do skip.
08 Instruction Register: The Instruction Register (IR) is output to the A buss. It is input from MDR via the B buss (instead of C buss) to avoid conflict with A and C buss usage during memory address resolution.

CHANGE: Drawing copy is redlined to show reference page #22 is deleted from off-page signal name "IR6".
Data and I/O Busses
12 Pull-Up Resistors: Three banks of 16 1K ohm resistors "pull up" the data lines of A, B, and I/O data busses to +5volts through the resistors. Outputs of multiple open-collector TTL gates can be connected a given buss line; such a connection is called "wired and". For use in a buss, The gates are managed so that all are kept in a high output state by default, and only one gate at a time is enabled to present its possibly low output state to the buss line (low pulling the buss voltage to near 0v through the gate's output transistor.

In the Other-1, NAND open-collector gates are used to manage output to busses: e.g., the "(low)IR out" control signal keeps IR latches data off (all NAND outputs high) the A buss while the control signal is high, only allowing the IR contents to be presented to the A buss when the control signal is low.

04 I/O Data Buss: The I/O Data Buss provides for 16 bit parallel data transfers from and to the CPU A register and external devices connected to the I/O buss. The I/O Data buss is the data transfer portion of the I/O buss interface, which also includes the I/O control signals portion (see drawing 31 Input / Output Control). An I/O Instruction execution always has two data transfer phases: first, A Register data is placed on the I/O data buss and control signals (including device address) are sent for the device to capture the sent data; second, additional control signals tell the device to put its data (if any) on the data buss for optional loading into the A Register (based on a bit setting in the I/O instruction).
Data Manipulation
10 Function Generator: The function Generator consists of four 4-bit 74181 Arithmetic Logic Units (ALU) ganged together to perform 16-bit arithmetic and logical operations with contents of the A and B data registers as input operands. See the Operate Combine instruction description: the available functions shown are exactly those of the TI 74181 function table for active low data. Carry-in and carry-out connect to the Link Register where the value can be set or tested; an A=B output can also be tested (see Operate Test instruction and Drawing 24 Test Flags).

19 Function Generator Control: Function Generator Control sets up the ALUs for use by the Operate Combine instruction, memory reference instructions using A and/or B Registers, and CPU supporting arithmetic.

- Combine instruction: The COMBE2 signal is true (DEC, ANDC, ORC, INCR, from Drawing  17 Register Input Control, are all false during Combine execution), causing the Function Generator MODE, SEL, and CARRY IN inputs to be set directly from the corresponding Combine Instruction fields and the Link state.
- Memory Ref Instructions: Input Signal COMBE2 is false for all; thus MODE is false too.
-- For TDA, TDB, LDA, LDB, CPA, and CPB instructions and Front Panel display of registers (DEC, ANDC, ORC, INCR are all false for these),  CARRY IN is 0, and SEL is 1001 binary causing the ALUs to be set up for function Twos Complement Addition ("A PLUS B"), and allowing for pass-thru of A or B value if the other register's value is 0 or not on its buss.
-- For AND instruction the ANDC input is true, setting SEL to 0001 binary and CARRY IN true to give ALU function "AB", where the MDR contents from memory are put on the B buss.
-- For IOR instruction the ORC input is true, setting SEL to 1011 binary and CARRY IN is false to give ALU function "A+B", where the MDR contents from memory are put on the B buss.

- CPU supporting arithmetic:
--  Signal INCR is used to increment the IC, AR, and MDR by setting SEL to 1011 binary and CARRY IN true to give ALU function "A+B PLUS 1" where one operand is not on a buss (=0).
-- Signal DEC is used to decrement the MDR by setting SEL to 0000 binary and CARRY IN false to give ALU function "A MINUS 1" where the MDR is on the A buss. (See drawing 17 Register Input Control for signals DEC, ANDC, ORC, and INCR.)

- NOTE: Although Arithmetic/Logical result flags SIGN POS, ZERO, and OVERFLOW can potentially be modified for any of the Function Generator modes, such results are captured only for instructions TDA, TDB, LDA, LDB, and OPR Combine with Mode (M) bit 11 set to Arithmetic Mode, as controlled by signal (low)CARRY ENABLE into Drawing 24 Test Flags.

09 Shift Register: The data shift register consists of four 74194 4-Bit Bidirectional Universal Shift Registers ganged together to form a 16-bit parallel input (F0 - F15) & output (C0 - C15) shift register, with a shift right serial data input (RIGHT IN), and a shift left serial data input (LEFT IN).

The "active-low" outputs (low)F0 through (low)F15 from the Function Generator (Drawing 10) are inverted to "active-high" F0 through F15 for input to the shift register. The outputs C0 through C15 of the shift register comprise the single data source of the C-buss.

The Clock (SR CLOCK) rising edge works with established Mode inputs (S0, S1) as follows:
- S0&S1=any,  clock low  => no change to register content and output
- S0=0, S1=0, clock any  => no change to register content and output
- S0=0, S1=0, clock rise => no change to register content and output
- S0=1, S1=0, clock rise => shift contents right one & shift in RIGHT IN value, new contents appear at outputs (C0 - C15)
- S0=0, S1=1, clock rise => shift contents left one & shift in LEFT IN value, new contents appear at outputs (C0 - C15)
- S0=1, S1=1, clock rise => inputs (F0 - F15) latched into register and appear at outputs (C0 - C15)

The input signals RIGHT IN and LEFT IN are supplied from logic on the Drawing 11 Link Register which: rotate the shift register contents including the link or not; shift in ones, zeros, or a link value. The outputs C0 and C15 are supplied as shift-out values to the Drawing 11 Link Register logic to rotate shift register contents, including the link or not.

21 Shift State Generator: This logic holds the CPU in the execution cycle E2 while the number of shifts/rotates is performed as specified in count (IR6-IR8) and include-link (IR13) fields of the OPR Shift instruction (where include-link = 1 adds one to the effective count).

Note: All the Operate instructions (Combine, Shift, Test, Miscellaneous) use two E cycles, normally one clock period each: E1 for incrementing the IC, and E2 for the instruction operation. The Shift instruction has the CPU wait in E2 while additional clock cycles are used to shift/rotate as needed.
The logic steps sequentially through three "states":

- set at the end of E1, and true for only the first clock cycle of E2...
- sets the CPU WAIT state, suspending it in execution cycle E2
- initialize (reset) the 7493 4-bit binary shift counter to 0 (only 3 bits used)

- true during count or count+1 clocks
- starts at end of ST1
- allows binary shift counter to count up as long as it does not equal the value of count (IR6-IR8)
- when counter value equals the instruction count, signal SAME becomes true, ST2 becomes false, and ST3 becomes true
- signals (low)SAME and IR13 (include-link) allow count or count+1 shift clocks (signal SR CLOCK in drawing 25 Shift Register Control) into the Shift Register.

- loads the shifted output of the shift register into A or B by activating (low)OPR A In or (low)OPR B IN, based on dest value (IR9-IR10) in the instruction (drawing 22 OPR Transfer Control).
- ends WAIT state (drawing 26 Major Cycle Control), allowing E2 to complete.

25 Shift Register Control: This logic sets up the data Shift Register to parallel load or serial shift, shift or rotate, and move data to right or left direction, as selected by the Operate-shift instruction control fields.

Only when the current instruction is Operate-shift, and the shift state is ST1 or ST2 (drawing 21 Shift State Generator), are the output direction control signals S0 and S1 to the Shift Register set to a shift direction right or left based on instruction field "dir" (IR12); otherwise they are both set high to select parallel data load.
The input signal IR13 (instruction field "inc") is used, if true, to select "count"+1 shift clocks, and include the Link Register in rotates by generating the signal ROTLWL (rotate left with link) or ROTRWL. Otherwise there are "count" shift clocks, and the link is not included in rotates, since neither signal ROTLWL nor ROTRWL is generated.

11 Link Register: The Link Register is a one-bit data register consisting of a single 7474 flip-flop at location 22F. Data routing logic provides serial data input from (C0, C15) or output to (RIGHT IN, LEFT IN) the data buss Shift Register (Drawing 09), and arithmetic carry input from (CARRY OUT) or output to (CARRY IN for OPR Combine) the data buss Function Generator (Drawing 10). Its value can be set and tested directly from program instructions.

The Link Register has two independent functions:

 - Working with the Operate-Combine instruction: Save arithmetic carry output from the Function Generator, and later provide the saved carry values to the Function Generator, primarily in support of multiple precision arithmetic operations. Also provide program settable carry to the Function Generator to allow direct program access to all Mode zero (M=0) ALU functions (see "Instruction Types" section above for "Operate Instruction: Combine" details sheet).
 During the Operate-Combine instruction, output signal LINK or (low)LINK may be available at the Function Generator as CARRY IN (Drawing 10), depending on the state of instruction bits 7 & 8 ("carry in") - see Drawing 19 Function Generator Control. Later during the instruction, input signal LCLOCK will latch into the LINK register the arithmetic operation result signal CARRY OUT value (picked from several inputs by signal LOAD LINK) from the Function Generator.
 - Working with the Operate-Shift instruction: Provide a serial bit insertion, modification, and test capability for data word shift and rotate operations. The Link Register control signals related to shift and rotate operations are discussed for Drawing 23 Link Control.
23 Link Control: This logic enables the Link Register to load the carry-out of the Function Generator for some arithmetic operations, and determines how the Link Register participates in Operate-shift instruction shifts and rotates.

For carry-out capture from the Function Generator:
- Signal (low) CARRY ENABLE is true when the IR contains an instruction expected to produce an arithmetic data result: LDA, LDB, TDA, TDB, and OPR Combine with Mode (M) bit 11 set to Arithmetic Mode.
- (low)CARRY ENABLE allows a clock pulse at output signal LCLOCK at E Cycle E2 for Operate-combine, or at E3 for LDA, LDB, TDA, and TDB (when the Function Generator CARRY OUT is available): LCLOCK being used to load the Link Register.

For clocking the Link Register during the Operate-shift instruction:
- no clocks are allowed to the LCLOCK (used to load the Link Register) if IR13 (instruction field "inc") is false, so the Link Register won't be modified during shifts or rotates.
- if IR13 is true ("inc" = 1), LCLOCK gets "count" clocks gated by ST2, and another clock unless IR14 and IR15 ("slink") are both false ("leave link" alone case). This allows the Link Register to be loaded with an initial value, then included in rotates.

For determining how the Link Register participates in shifts and rotates:
The 74155 decoder at location 17B is connected as a dual 2-to-4-line decoder, with the same two lines IR14 and IR15 ("slink") being decoded to each section, and IR13 ("inc") being used to enable one section or the other.  
- When "inc" (IR13) =0, the "1Y1-1Y4 outputs of the 74155 are enabled, and "slink" decodes to one of the output signals (low)ROTATE NO LINK, SHIFT IN LINK VALUE, SHIFT IN ZEROS, SHIFT IN ONES, reflecting the corresponding instruction options; similarly "inc"=1 is decoded.
- Moreover, input signal (low)ST1 enables the "2Y1-2Y4" 74155 for the data Shift Register initialization period only, to allow only an initial Link value to be set ("inc"=1), while the (low)ST2+3 input signal enables the "1Y1-1Y4" 74155 outputs during all "count" clock pulses to LCLOCK.

CHANGE: Drawing copy redlined to show:
- Signal E3F5/24 is disconnected from AND gate pin 16C9
- Signal E3F9/24 is disconnected from AND gate pin 16C5
- AND gate pin 16C6 is disconnected from NOR gate pin 16A11
- Signal E3F5/24 connected to NOR gate pin 16A9
- Signal E3F9/24 is connected to NOR gate pin 16A8
- NOR gate pin 16A10 is connected to INVERT gate 18A5
- INVERT gate pin 18A6 is connected to NOR gate pin 16A11

22 OPR Transfer Control: This logic controls data flow from A and B registers as sources, and into A and B registers as destinations for the Operate instruction Combine, Shift, and Miscellaneous types.

For the Operate Miscellaneous Load-Switch-Word case, the switch word contents need to get loaded into the A register: The input signal E2F24 has been formed from E-cycle time E2 and the OPR instruction type in the IR (see drawing 15 E Cycle Sequencer). It now combines with inputs (low)MISC operate-instruction-type and (low)IR6 (the MISC instruction load-switch-register bit) to give output signal (low)LDSW. This signal goes on to the drawing 16 Transfer Function Generator, where its name is changed to "(low)SWR->A", then on to drawing 17 Register Input Control, where it generates signals "(low)SWRout" and "(low)Ain" (during time E2).

The Operate Combine and Shift instruction types both have data register source and destination bits:
- Combine source: IR6 (inhibit A, i.e., force to 0)
- Shift source: IR11 (from - 0 is A, 1 is B)
- Combine and Shift destinations: IR9 & IR10 (A whenever 1R9 is 1, B whenever IR10 is 1)
For these cases, the desired register content control output signals (low)OPR A IN, (low)OPR B IN, (low)OPR A OUT, and (low)OPR B OUT are generated during E2 Cycle time for Combine, or during ST3 E cycle time (see drawing 21 Shift State Generator) for Shift.

The above-mentioned input signal E2F24 is also combined with Operate instruction type (low)COMB to give output signals "COMB E2" which are used to set the ALU mode and control link usage during the Combine instruction E2 Cycle.

CHANGE: Drawing copy redlined to show:
-  signal "IR6" removed, and replaced with a connection from OR gate pin 12D13 to gate pin 14A2.
- AND gate pin 13A12 is disconnected from AND gate pin 13A1, etc.
- NAND gate pin 14A3 is disconnected from NAND gate pin 12E3.
- NAND gate pin 13B11 is connected (also) to NAND gate pin 12E3.

Data Test
24 Test Flags: The signal (low)CARRY ENABLE is true when the IR contains an instruction expected to produce an arithmetic result (see Drawing 23 Link Control). It is combined with signal IN TIME to capture the states of the Function Generator (Drawing 10) sign bit signal F0 and equality signal A=B into latches SIGN POS and ZERO; also captured into latch OVERFLOW are the register sign bits A0, B0, and Function Generator sign bit F0 - combined to detect arithmetic overflow. The latches retain the captured states until the next instruction expecting an arithmetic result is executed.

Several memory reference instructions, ISV, ISA, STACK, & POP, increment a memory data or address value and skip the next instruction if a limit - zero or an equality comparison - is (or is not) reached. The E cycle timing timing signals for these instructions (see Drawing 15 E Cycle Sequencer) are combined with IN TIME to capture the Function Generator equality signal A=B into the INT ZERO latch (INT means "Internal" here) for later use in the instruction to control the skip action: depending on the instruction, signal (low)V/AT<>0, (low)ST<>0, or (low)PT<>0 is produced (these are inputs to Drawing 15 E Cycle Sequencer).

20 OPR Test Select: The selection bits 6 - 10 of the Operate Test instruction determine which CPU flags will be included in the Test skip action (testing a flag does not modify the flag):

IR6  - Positive arithmetic result
IR7  - Link set
IR8  - Overflow/Underflow arithmetic result
IR9  - Zero arithmetic result
IR10 - Interrupt mode enabled (interrupts function is not implemented)

Control bits 14, 15 determine the type of skip-next-instruction  action:
IR14 - 0: action is skip, else no skip;
           1: action is no skip, else skip
IR15 - 0: action if any selected test flag is true
           1: action if all selected test flags are true

The output signal (low)TSKIP is used in Drawing 15 E Cycle Sequencer to generate signal (low)E2F3, input to 16 Transfer Function Control to generate (low)IC INC, an input to 17 Register Input Control.

Manual Control
View of Other-1 Front Panel and Keyboard.  Typical panel functions for 1965-75 minicomputers.

Indicators (all present the current running or paused/halt state of the listed signals):
- L: LINK (14C12)
- 0-15: F0 - F15 (of the Function Generator - i.e., the un-shifted output to the C Buss)
- POS, ZERO, OFLW, INTEN: SIGN POS (13C5), ZERO (13D5), OVERFLOW (13D9), INT EN (n.c.) (test flags)
- ICYC: I CYC (20E5)  (i. e., CPU in the instruction fetch phase)
- RUN: RUN (23D5) (CPU running at clock speed)
- WAIT: WAIT (20E9) (CPU paused or halted in manual mode)

Controls - General:
- The RUN, CYC, and STEP buttons control the RUN and Halted state of the CPU: all other controls are active only in the Halted state.
- The system CPU is halted upon power up, following Single Step (STEP) or Single Cycle (CYC) button activation, and by the Halt Instruction.

Selector Switch: Display the selected register while the CPU is halted (See Drawing 30 Display Selection).

Toggle switches 0-15: Switch Register - Program readable when CPU is running (including during CYC, STEP); also used to load start address for EXAM or DEP functions and instruction/data values for DEP function when CPU is halted.

These buttons allow manual memory content exam or modification without executing program instructions (see Drawing 27 Manual Data Control):
- ADD: Load Address Register with starting address from Switch Register, when CPU is halted.
- DEP: Deposit Switch Register value to memory at address in Address Register, and increment Address Register, when CPU is halted.
- EXAM: Load Memory Data Register from memory at address in Address Register, and increment Address Register, when CPU is halted.

This button performs system reset (see Drawing 28 Reset):
- RST: system reset of most state logic to initial settings, when CPU is halted.

These buttons manipulate the RUN state of the CPU to control the rate of instruction execution (see Drawing 29 Run / Single Cycle / Single Step):
- RUN: Allow the always-running system clock output (2MHz square wave) to pass on to CPU instruction execution logic.
- CYC: If the CPU is running, halt the CPU at the end of the current execution cycle; if it already halted, allow a single system clock cycle to pass to CPU instruction execution logic.
- STEP: If the CPU is running, halt the CPU at the end of the current instruction execution phase; if it is already halted, allow system clock cycles to pass to CPU till the end of the next instruction execution phase.

The keyboard is connected as an input device on the I/O bus, and is functional only under program control.

27 Manual Data Control:  Manual Data Control handles the Load Address, Deposit, and Exam front panel push-button switch functions. These switches are enabled for use only when the RUN signal is false (i.e., the CPU is halted).
- Load Address push-button copies the contents of the Switch Register (SW) bits 2-15 into the Address Register (AR).
- Deposit push-button writes the contents of the SW into memory at the current AR address, then increments the AR address.
- Exam push-button reads the contents of memory at the current AR address into the Memory Data Register (MDR), then increments the AR address. (If the panel Display rotary switch is set to "MD" (MDR), the MDR contents are displayed on the 16 LED data readout on the Panel.)

If RUN is false, pressing any of the three push-buttons enables system clock signal CLC to appear at output signal MAN CLK. The latter clocks the signal false signal (low)MAN into the SER IN input of the 7496 5-bit shift register, immediately making (low)MAN true, so that one True bit propagates through the shift register on subsequent MAN CLOCK cycles, appearing at shift register outputs 0 - 4 in order. When the bit reaches output 4, signal MAN CLK is disabled, and (low)MAN becomes false. Later when the push-button is released, the shift register is cleared.

While the bit is moving across shift register outputs 1 - 3, it is combined with the push-button signals to enable in turn some of the output signals MAN21, MAN25, MAN16 MAN23, MAN12, and MAN10. These signals are input to the Transfer Function Generator (drawing 16) to cause a series of register transfers effecting the desired push-button action, as follows:

Load Address:  shift out 1  -->  MAN21  -->  SW->MDR
                        shift out 2  -->  MAN16  -->  MDR->AR
                        shift out 3  -->  MAN10  -->  AR->IC

Deposit:          shift out 1  -->  MAN21  -->  SW->MDR
                       shift out 2  -->  MAN23  -->  MDR->mem
                       shift out 3  -->  MAN12  -->  AR inc

Exam:              shift out 1  -->  MAN25  -->  mem->MDR
                       shift out 2  -->  MAN12  -->  AR inc

28 Reset / Iin: Reset / Iin logic handles the System Reset front panel push-button. The Reset push-button is available for use only when the RUN signal is false (i.e., the CPU is halted).

The reset signal outputs:
- force CPU state flags E CYC to True; I CYC, WAIT, E OUT, I IN, and I OUT to False
- reset Shift Control state logic
- reset instruction fetch addressing and indirect addressing logic
- reset E Cycle Counter

29 Run / Single Cycle / Single Step: Run / Single Cycle / Single Step logic supports the corresponding front panel push-button switches Run, Single Cycle, and Single Step.

Notice that:
- While none of the buttons are pressed, the AND output pin 24C11 is low; a button depress causes a one clock-cycle wide high pulse to appear at 24C11 (releasing the button does not cause a pulse).
- Unless the current instruction is an Operate Miscellaneous Halt at the end of Execution phase, the AND input at 21D3 will always be high.
- As long as the Single Cycle or Single Step buttons are not pressed, the AND input at 21D4 will always be high.

The RUN flip-flop at 23d5 determines the run/halt state of the CPU.

Run push-button: If depressed, the RUN flip-flop will be set to RUN (if not already) by the high pulse at 24C11. The RUN output connected to the AND input 21D5 ensures the RUN flip-flop will now continue to be in the RUN state as long as the other AND 21D inputs remain high.

Halt Instruction: When executed, the Operate Miscellaneous Halt instruction will cause the OR output 19B6 (AND input 21D3) to go low at the end of the Execute phase, causing the RUN flip-flop RUN output to be clocked False. Once False, the output will stay that way even if the HALT instruction is removed (by single cycle or single steps) since the (low)RUN output connected to AND input 21D3 keeps the AND output low, until the Run push-button is pressed.

Single Cycle push-button: If depressed, the NOR input 23C11 will go high, and the AND input 21D4 go low, causing the RUN flip-flop RUN output to be clocked False, following the end of the one clock-cycle wide pulse also caused by the button push. Once False, it will stay that way, as in the case of the Halt Instruction, till the Run push button is pressed. However, pressing the Single Cycle push button with RUN output False, generates the one cycle wide pulse which sets RUN high for just one cycle.

Single Step push-button: Works like the Single Cycle push-button, except the RUN output is not set False till the E OUT (Execution phase end) input at 24C3 is high. So Single Step pushes with RUN output False cause an entire instruction to execute with each push

NOTE: I remember that the Single Cycle button would hang the CPU after a few pushes, so something wasn't working right, possibly related to the waits for memory accesses. The Single Step button worked just fine.

30 Display Selection: The Display Selection logic works with the front panel rotary switch to display the content of registers AR, IC, IR, MDR, A, and B on the front panel LEDs 0 through 15.

The panel LEDs 0-15 are physically wired to the inverted data outputs F0 - F15 (shown on drawing 09 Shift Register) of the Function Generator, always displaying the active-high output of the generator.

The CPU must be halted (RUN signal is false) to view the register content selected by the panel rotary switch. The selected (e.g. (low)DISP AR) register's output is then available when a push button action is not being handled (HOLD is false, MAN is false): the output is then input to the Register Input Control (drawing 17), where it is used to put only the selected register's output on the A or B buss continuously. From the description of drawing 19 Function Generator Control, the function generator is set to mode "A PLUS B" with carry-in = 0 for front panel display, so the LED display will show the register's content.

Input / Output Control
31 Input / Output Control: The I/O Control Logic provides signals on the I/O buss to manage data transfers and functions of an addressed device, and to obtain status from that device. Data transfers are between the addressed device and the A Register, as described for drawing 04 I/O Data Buss. Most of the control signals are to the connected I/O devices: (low)DEV1-DEV4 and (low)IOF1-IOF3 of the I/O instruction address a specific device and provide a function for the addressed device to perform. Timing signals (low)IOT1-IOT3 and (low)TIME indicate data-to-device and data-from-device times and provide function timing. A single input from the device, (low) I/O SKIP, allows the device to signal a condition, such as Busy, Done, or Ready, by causing the I/O instruction to skip: this signal is typically tied to a device-specific I/O instruction function code.
Addressing Control
13 Address Control: During Instruction Fetch (I Cycle), the Address Control logic loads the next instruction to be executed into the IR and resolves the effective address if it is a memory reference instruction.

The control signal "Iin" starts the I Cycle by executing the following transfer sequence, which gets the instruction pointed to by the IC from memory through the MDR and into the IR (see drawing descriptions for 16 Transfer Function Generator and 17 Register Input Control for how the "ADCTL" signals are converted to register transfers) in sequential steps:

ADCTL1  --> IC->AR
ADCTL2  --> mem->MDR

If the instruction is not a memory reference type (MREF=false), the I Cycle is complete and control signal "Iout" is generated.

If the instruction is memory reference (MREF true), address control bits 0 ("rel") and 1 ("ind") of the instruction copy still in the MDR are examined for what to do next...

rel: mdr bit 0 = 1; ind:  mdr bit 1 = 0 => relative direct addressing
ADCTL5  --> ARaddMDR(6-15)->AR

rel: mdr bit 0 = 0; ind: mdr bit = 0 => absolute direct addressing (in current page)
ADCTL6  --> MDR(6-15)->AR(6-15)

TBS for...

ADCTL7  --> (low)mem->MDR
ADCTL8  --> (low)ARaddMDR(6-15)->AR
ADCTL9  --> (low)MDR->AR
ADCTL10 --> (low)MDR(6-15)INC
ADCTL11 --> (low)MDR->mem

Instruction Fetch / Execution Cycle Control
26 Major Cycle Control: This logic manages the transition between Instruction Fetch (I) and Instruction Execution (E) phases, and provides a "wait" state for certain functions which take longer than a single clock period ("cycle") to complete.

The basic processing step for the Other-1 is the Execution Cycle (E Cycle) time, one CPU clock period (or clock "cycle") in length, and is the minimum time needed to put a data register's parallel content onto the A or B data buss, and load that content into another data register on the A, B, or C data buss.

The Instruction Fetch phase (or "I cycle") includes:
1) Get the next instruction address from the Instruction Counter (IC) into the Address Register (AR).
2) Obtain the addressed instruction from core memory through into the Memory Data Register (MDR).
3) Move the memory data into the Instruction Register, and
4) If the new instruction is a memory reference type, resolve its effective addressed data into the MDR or AR.
Major Cycle Control involvement:
-- Start I phase: input I IN Signal (drawing 28 Reset/Iin), triggered by input END Signal of previous completing instruction (drawing 16 Transfer Function Generator, sh 2). I IN also starts Address Control (Drawing 13) I Cycle processing.
-- End I phase: input an I OUT signal (from Drawing 13 Address Control) to start output signal E CTR CLOCK.

The Execution Phase is a series of E Cycles that includes:
1) Execution cycle E1, which increments the Instruction Counter for all instructions.
2) One or more E Cycles (E2 up to E13) of instruction-unique operations and register transfers.
Major Cycle Control involvement:
-- Start of Execution phase: begin E counter clock.
-- End of execution phase: The last instruction-specific E Cycle also generates an END signal.

Wait State:
The Wait State provides a common delay mechanism for Core Memory reads/writes and for data Shift Register shift operations, both of which take more than one processing step (single clock period) to accomplish. The Wait State stretches the current I or E processing step until the memory access or shift operation is complete.
- The core memory read/write cycle time is fixed at 8 microseconds. See the Magnetic Core Memory Logic page for a discussion of memory read/write. In Major Cycle Control, input signals MDR PASS MEM (from Drawing 17b Register Input Control) or MDR TO MEM (Drawing 16b Transfer Function Generator) start the wait, and MEM DONE (Drawing 35 Read Write Control) ends it.
- Since the Shift instruction allows a variable number of shifts/rotates, I decided to provide a separate control mechanism for it, rather than use the E cycle scheme, which provides a unique but static series of steps for each of the other instruction types. See Drawing 21 Shift State Generator for a description of the Shift Instruction's wait during E2 cycle for the shift actions. In Major Cycle Control, input signal ST1 starts the wait; input signal ST3 ends it.

- There are no off-page connections for signals I CYC and E CYC.

Execution Cycle Control
18 IR(2-5) Decode: The IR Decode logic (four 74155 ICs) provides 16 separate signal lines for the 4-bit instruction code (IR2 - IR5), one for each instruction type, the decoded one being active low.. It also decodes 4 signal lines for the types of the Operate instruction specified in IR(0 -I R1), one of which will be active low if "(low)OPR" is true. Finally, it decodes signal lines for pairs of instructions, which have some common Execution cycles, e.g., "(low)TAD" for the TADA and TADB instructions.

The decoded signals for an instruction will be true for as long as the instruction remains in the IR - which will be for its entire Execution phase.
14 E Cycle Counter and Decode: Two 74151 decoders, driven by the 4-bit counter at location 4E, provide 13 decoded output lines (low)E1 through (low)E13, the line which is active low advancing sequentially as the counter advances. The counter is reset by system-reset, or by signal ADCTL1 which is generated when the previous instruction reaches the last E cycle (always 13 or fewer E cycles) of its execution phase.

15 E Cycle Sequencer: The E Cycle Sequencer maps each E Cycle to the instructions which will perform the same transfer function at that E Cycle. There may be multiple mappings for each E cycle, each mapping containing different instructions. For example, all instructions need to increment the IC right away, so E1 maps to sequencer output signal "E1F3" which will generate a transfer signal "(low)IC INC" at E1 cycle time (on drawing 16 Transfer Function Generator) for every instruction.

A less trivial example: After E1 the cycle, instructions LDA, LDB, TADA, TADB, ISZV, ISZA, STACK, and POP all need to retrieve their data reference from memory as the next step: so input instruction signals "(low)TAD", "(low)LD", "(low)ISZ", and "(low)LIFO" are all combined to sequencer output signal "(low)E2F25" which will generate a transfer signal "(low)MEM -> MDR" (on drawing 16 Transfer Function Generator) at E2 cycle.

16 Transfer Function Generator:
The Transfer Function Generator builds unique output transfer function signals for all sources that need to perform each transfer function type. The sources are the E Cycle Sequencer, Address Control, and Manual Data Control. The transfers are between memory and MDR, or between other registers on the data busses, possibly involving data modification in the Function Generator (ALU). These transfer function signals are then input to the Register Input Control (drawing 17).

All instructions also generate the output signal "END" with their last E cycle to mark the end of the instruction's Execution phase.

CHANGE: Drawing copy (sh2) redlined to show:  Signal name "E4F20/24" should be "E2F20/24"

17 Register Input Control: Register Input Control logic typically converts each input Transfer Function signal (drawing 16) into a register output control signal and a (possibly other) register input control signal that will occur on the same E cycle. (Notice the organization of output signals across the top of the drawing: Output control signals for all the registers, followed by input control signals for all registers ANDed with a strobe-in signal "TIME IN")

Here is an example with the E cycles needed for instruction LDA, starting with the E Cycle Sequencer:
Cycle E1:  [all] -> E1F3 -> (low)IC INC -> IC OUT, IC IN, INCR

Cycle E2:  LD  -->  (low)E2F25   -->  "(low)mem->MDR"  -->   MDR PASS MEM,  MDR IN (0-5),  MDR IN (6-15)
Cycle E2:  LDA  -->   E2F19       --> (low) A CLEAR        -->    (low)A IN

Cycle E3:  LDA  -->  E3F5/24  -->  "A ADD MDR->A", END  -->  (low)A OUT, (low)MDR OUT B, (low)A IN

in E cycle 1, the IC is incremented
In E cycle 2, the memory data is read into the MDR; also A is cleared (A IN without anything OUT on A or B buss gives 0 to input to A).
In E cycle 3, the MDR data is OUT on B and IN to A (since A is 0, MDR-data ADD A equals MDR-data)

Also in cycle 3, an "END" signal was generated in the Transfer Function Generator: this signal is sent to "26 Major Cycle Control" where it is used to end the Execution phase of this instruction.