Magnetic Core Memory Logic Details
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Core Memory Logic Drawings
About the Drawings
Photographs of the original OTHER-1 logic drawings related to the implementation of the Core Memory are presented here. The drawings were done with pencil on tracing paper with orange grid lines Though most had the grid on the reverse side, black and white copies were still hard to read, so the photos help a lot.
Usually a drawing was done following the implementation using design sketches and prepared wiring lists and limited static testing with power applied. A Xerox of the drawing was made, and any subsequent red-line changes were made to the copy and the wiring lists, but not to the original tracing. Not many red-lines were necessary, and the only modifications to the originals here are to the Inhibit Drivers Logic and the Read / Write Control Logic drawings.
Reading and Navigating the Drawings
All of the OTHER-1 logic circuit drawings and physical board layouts which have been uploaded to this site are located in the Photo Gallery as albums:
- Core Memory Logic
- Other-1 Board Layouts
- CPU Logic
All of the Core Memory and some of the CPU logic circuit drawings also appear on this page. Explanatory tables and diagrams related to the logic drawings will appear on this page only. There are about 50 logic circuit drawings for the OTHER-1, some multi-sheet.
The Board Layouts are wiring-side views of the of the physical locations of the integrated circuits (ICs) used in the computer's construction. Most of the ICs are small scale digital TTL circuits, 14 or 16 pin, and are plugged into wire-wrap sockets mounted on pre-drilled phenolic boards. The Board Layouts are marked with a coordinate system - numbers 1 to 25 across the top and letters across the left side - the letters are unique for the four large 6" x 17" circuit boards:
- A, B, C, D, E --Instruction Control Logic Board - CPU
- F, G, H, J, K -- Registers Board - CPU
- L, M, N, P, S -- X-Y Drivers Board - Memory
- T, U, V, X, Y, Z -- Inhibit Drivers Board - Memory
All of the OTHER-1 logic circuit drawings and physical board layouts which have been uploaded to this site are located in the Photo Gallery as albums:
- Core Memory Logic
- Other-1 Board Layouts
- CPU Logic
All of the Core Memory and some of the CPU logic circuit drawings also appear on this page. Explanatory tables and diagrams related to the logic drawings will appear on this page only. There are about 50 logic circuit drawings for the OTHER-1, some multi-sheet.
The Board Layouts are wiring-side views of the of the physical locations of the integrated circuits (ICs) used in the computer's construction. Most of the ICs are small scale digital TTL circuits, 14 or 16 pin, and are plugged into wire-wrap sockets mounted on pre-drilled phenolic boards. The Board Layouts are marked with a coordinate system - numbers 1 to 25 across the top and letters across the left side - the letters are unique for the four large 6" x 17" circuit boards:
- A, B, C, D, E --Instruction Control Logic Board - CPU
- F, G, H, J, K -- Registers Board - CPU
- L, M, N, P, S -- X-Y Drivers Board - Memory
- T, U, V, X, Y, Z -- Inhibit Drivers Board - Memory
On the Memory board drawings, each rectangle depicting an IC location is marked
the IC type (e.g. 74155), and typically (except the Inhibit Drivers
Board) the number of pins (14, 16, 24), and unused logic gates in the IC
(usually 0). Along the bottom, the general purpose of each group of ICs
is indicated, and loosely relates to the name of the associated Logic
diagram.
See IC Reference page for links to IC datasheets.
See IC Reference page for links to IC datasheets.
On a typical Logic Circuit Drawing,
each used logic component is separately depicted, regardless of of how
many such components are in the same IC package. The symbols used for
the logic components are usually those appearing in the IC maker's
handbook or data sheets (typically Texas Instruments). Off-diagram
connections are labelled: the label name indicates the True or Active
sense of the signal: an over-score on the name indicates the signal is
True or Active when logical "0" or "low" (0 volts), lack of the
over-score indicates True or Active when logical "1" or "high" (3
volts).
Each logic component symbol will contain a number+character label inside
(e.g., "5T") indicating the coordinates of it's containing IC on a
Board Layout. (Other notations inside the symbol are generally those of
the IC maker. I have marked some logic symbols "OC" to indicate an
open-collector output.) Around the outside of the symbol, at the wiring
connection points, are the IC pin numbers used for this logic component.
Several logic components sharing the same IC package will have the same
IC coordinates label, but will have different pin numbers. Connections
across a multi-sheet drawing are labelled and the connections drawn with
arrows: "-->" or ">--".
The "A (X or Y) Core Drivers", "B (X or Y) Core Drivers, and "Inhibit Drivers" logic circuit drawings are atypical, in that they show a representative circuit that is actually repeated, based on associated Tables providing additional IC position and wiring information. See the sections (below) on these drawings for more detail.
OTHER-1 Interface between CPU and Core Memory
2 Memory Data Register
The Memory Data Register (MDR) is the interface buffer for data moving between the CPU and core memory. It is one of the eight 16-bit data registers in the CPU, connected together by three data busses.
The Memory Data Register (MDR) is the interface buffer for data moving between the CPU and core memory. It is one of the eight 16-bit data registers in the CPU, connected together by three data busses.
At CPU:
There are three 16-bit CPU data Busses: A buss, B buss, and C buss:
- Registers A, B, IC, IR, AR, Switch, MDR, and I/O Data: output to the A and/or B buss
- A buss and B Buss data are combined or selected at the ALU, passed through the Shift Register, and fed into the C Buss
- C Buss data: input to A, B, IC, AR, MDR, I/O Data
(- B Buss data is input to IR)
There are three 16-bit CPU data Busses: A buss, B buss, and C buss:
- Registers A, B, IC, IR, AR, Switch, MDR, and I/O Data: output to the A and/or B buss
- A buss and B Buss data are combined or selected at the ALU, passed through the Shift Register, and fed into the C Buss
- C Buss data: input to A, B, IC, AR, MDR, I/O Data
(- B Buss data is input to IR)
At Core Memory:
- MDR data is output to Inhibit Drivers for write to memory: (low) signals MDR BIT 0 thru MDR BIT 15 into Inhibit Control drawing multiplexers at 1T, 3T, 5T, and 7T.
- MDR data is input from Sense Amplifier data buffers after read from memory: (low) signals MEMR0 thru MEMR15 from Sense Amplifiers / Read Buffer drawing.
- MDR data is output to Inhibit Drivers for write to memory: (low) signals MDR BIT 0 thru MDR BIT 15 into Inhibit Control drawing multiplexers at 1T, 3T, 5T, and 7T.
- MDR data is input from Sense Amplifier data buffers after read from memory: (low) signals MEMR0 thru MEMR15 from Sense Amplifiers / Read Buffer drawing.
1 Address Register
The Address Register (AR) is the interface buffer for addresses, specified by the CPU, of data to be read or written by the core memory.
The Address Register (AR) is the interface buffer for addresses, specified by the CPU, of data to be read or written by the core memory.
At CPU:
- The AR is loaded from IC, Switch, or MDR
At Core Memory:
- The 12-bit AR address output always available at the core memory X-Y Drivers via six 74155 decoders shown on the Core Driver Select drawing (just below).
- Redlines to a copy of this drawing show that I later added 2 latches (at 3K) and buffers (at 4K) to handle input bits C2, C3, and output bits B2, B3, using existing control signal "AR IN(4-5)" at gate output 1F4.
My design intent was to initially address 4096 (4K) words of the Spectra 70 core stack, with an option to expand the addressing to 16K words later, implementing only partial initial support for 16K. The largest address needed in AR to address 4K is 7777 (octal), which sets AR4-15 to ones. AR2-3 would be used to address to 16K; since I never actually expanded core stack use from 4K to 16K, AR2 and AR3 are always 0, and the decoders at 10N and 16N are not needed.
- The AR is loaded from IC, Switch, or MDR
At Core Memory:
- The 12-bit AR address output always available at the core memory X-Y Drivers via six 74155 decoders shown on the Core Driver Select drawing (just below).
- Redlines to a copy of this drawing show that I later added 2 latches (at 3K) and buffers (at 4K) to handle input bits C2, C3, and output bits B2, B3, using existing control signal "AR IN(4-5)" at gate output 1F4.
My design intent was to initially address 4096 (4K) words of the Spectra 70 core stack, with an option to expand the addressing to 16K words later, implementing only partial initial support for 16K. The largest address needed in AR to address 4K is 7777 (octal), which sets AR4-15 to ones. AR2-3 would be used to address to 16K; since I never actually expanded core stack use from 4K to 16K, AR2 and AR3 are always 0, and the decoders at 10N and 16N are not needed.
34 Core Driver Select
The Core Driver Select logic converts the 12 bit address from the AR into two pairs of core driver selection signals: 6 bits to the pair for the X drivers, and 6 bits to the pair for the Y drivers. Each pair of 16 selection signals is divided into two equal parts: 8 for selecting one of eight drivers for the A-side (labelled side) of the core stack, and 8 for selecting one of eight drivers for the B-side.
The Core Driver Select logic converts the 12 bit address from the AR into two pairs of core driver selection signals: 6 bits to the pair for the X drivers, and 6 bits to the pair for the Y drivers. Each pair of 16 selection signals is divided into two equal parts: 8 for selecting one of eight drivers for the A-side (labelled side) of the core stack, and 8 for selecting one of eight drivers for the B-side.
The conversion is done by 74155 decoders which are configured for 3-line (3 digit binary value input) to 8-line (one of 8 outputs selected (low)) decode:
- a "low" at the 1G and 2G inputs of the decoder enable it to produce a selected output
- AR13 thru AR 15 decode into (low) signals AX00 thru AX07
- AR3 and AR10 thru AR12 decode into (low) signals BX00 thru BX07
- AR7 thru AR9 decode into (low) signals AY00 thru AY07
- AR2 and AR4 thru AR6 decode into (low) signals BY00 thru BY07
- a "low" at the 1G and 2G inputs of the decoder enable it to produce a selected output
- AR13 thru AR 15 decode into (low) signals AX00 thru AX07
- AR3 and AR10 thru AR12 decode into (low) signals BX00 thru BX07
- AR7 thru AR9 decode into (low) signals AY00 thru AY07
- AR2 and AR4 thru AR6 decode into (low) signals BY00 thru BY07
The Core Stack
As described in my Byte article, the Spectra 70 stack consists of 128 (Y) by 136 (X) words by 18 bits/word. Each of the 18 bit planes is organized into four 64 x 68 bit quadrants with four sets of sense lines (loops) parallel to the Y select lines, one set per quadrant. I used 64 by 64 words from one quadrant. There are also 8 inhibit lines per bit plane, parallel to the X select lines.
The X and Y select lines are brought out to double-side PC board edge connection fingers on either end of the stack (connectors 1A-8A, 1B-8B). J1-J4 are for the inhibit lines, J1-J2 are for the sense lines.
As described in my Byte article, the Spectra 70 stack consists of 128 (Y) by 136 (X) words by 18 bits/word. Each of the 18 bit planes is organized into four 64 x 68 bit quadrants with four sets of sense lines (loops) parallel to the Y select lines, one set per quadrant. I used 64 by 64 words from one quadrant. There are also 8 inhibit lines per bit plane, parallel to the X select lines.
The X and Y select lines are brought out to double-side PC board edge connection fingers on either end of the stack (connectors 1A-8A, 1B-8B). J1-J4 are for the inhibit lines, J1-J2 are for the sense lines.
Core Drivers for the Stack
Only 4K words implemented
To the right is the X-Y Drivers Board layout. Note that some filled-in IC slot positions are marked "4K" while others are not. The positions not marked "4K" were reserved for a 16K expansion that was never implemented. In particular, the following 16K expansion slots are not implemented nor occupied by ICs or sockets:
- L1 - L4, and L22 - L25
- N1 - N4, and N22 - N25
- columns 6 and 7, and columns 19 and 20
Compare with photo above, which shows the X-Y Drivers board tilted up (bottom row S towards camera).
To the right is the X-Y Drivers Board layout. Note that some filled-in IC slot positions are marked "4K" while others are not. The positions not marked "4K" were reserved for a 16K expansion that was never implemented. In particular, the following 16K expansion slots are not implemented nor occupied by ICs or sockets:
- L1 - L4, and L22 - L25
- N1 - N4, and N22 - N25
- columns 6 and 7, and columns 19 and 20
Compare with photo above, which shows the X-Y Drivers board tilted up (bottom row S towards camera).
32 A (X or Y) Core Drivers - Reading the drawing
The A(X or Y) Core Drivers Logic drawing is shown to the left. The "A" in the name means that these drivers connect to the X or Y select lines at the top (side with the manufacturer's label) of the stack; the "B" drivers connect at the bottom of the stack.
Note that the "16K only" components and table entries at "N" and "L" are not implemented.
The drawing shows a representative core driver at "S" and diode arrays at "M" and "P". The table expands on this view, showing that there are actually four X core drivers (at 4S, 3S, 2S, 1S) and four Y drivers (at 22S, 23S, 24S, 25S); similarly for the diode arrays.
Table values "a", "m", "n" are used to specify the signal names applying to an actual IC component. For instance the first two entries "a, m, n = X, 0, 0 and X, 0, 1" (COL 4 entry) for the Core Driver IC at 4S gives its input signal names:
X DRIVER SOURCE
(low) AX00 <--- from Core Driver Select logic
(low) X READ
(low) X WRITE
(low) AX01 <--- from Core Driver Select logic
X DRIVER GROUND
Continuing the the example for the "COL 4" entry case, the 8 X memory drive lines (0 thru 7) connecting to the diode array pins (2 3 4 7 8 9 11 12) at 4P, and the X memory drive lines (8 thru 15) connecting to the array at 4M are obtained.
Note that the Y drivers will have "Y" Core Driver Select names , and that Y drive lines assignment numbers to the Y diode arrays are identical to those given to the X diode arrays.
Note that the "16K only" components and table entries at "N" and "L" are not implemented.
The drawing shows a representative core driver at "S" and diode arrays at "M" and "P". The table expands on this view, showing that there are actually four X core drivers (at 4S, 3S, 2S, 1S) and four Y drivers (at 22S, 23S, 24S, 25S); similarly for the diode arrays.
Table values "a", "m", "n" are used to specify the signal names applying to an actual IC component. For instance the first two entries "a, m, n = X, 0, 0 and X, 0, 1" (COL 4 entry) for the Core Driver IC at 4S gives its input signal names:
X DRIVER SOURCE
(low) AX00 <--- from Core Driver Select logic
(low) X READ
(low) X WRITE
(low) AX01 <--- from Core Driver Select logic
X DRIVER GROUND
Continuing the the example for the "COL 4" entry case, the 8 X memory drive lines (0 thru 7) connecting to the diode array pins (2 3 4 7 8 9 11 12) at 4P, and the X memory drive lines (8 thru 15) connecting to the array at 4M are obtained.
Note that the Y drivers will have "Y" Core Driver Select names , and that Y drive lines assignment numbers to the Y diode arrays are identical to those given to the X diode arrays.
33 B(X or Y) Core Drivers - Reading the drawing
The B (X or Y) drawing at the left shows the "B" core drivers, which connect to the bottom of the core stack.
Note that the "16K only" components and connections shown in the table are not implemented.
The drawing shows two representative core drivers at P and N, and two representative diode arrays at M and L: Similar to the method used for the A drivers, this drawing table expands the view to show four X drivers (at 9P, 9N, 8P, 8N) and four X diode arrays (at 9M, 9L, 8M, 8L) , four Y drivers (at 17P, 17N, 18P, 18N), and four Y diode arrays (at 17M, 17L, 18M, 18L).
Signal names are built for B as for the A drivers above: in the "COL 9" entry, for example, "a n m" = "X 0 0" builds the signal name (low) BX00 at the 9P driver, pin 3; "a n m" = "X 0 1" builds the signal name (low) BX01 at the 9P driver, pin 14.
The table Drive Line area shows that two select lines are wired to each diode array pin: continuing the "COL 9" example, B X core stack select lines 0 and 8 connect to diode array 9M pin 2, lines 16 and 24 connect to 9M pin 3, etc.
As for the A drivers drawing, note for this B drawing that the Y drivers will have "Y" Core Driver Select names , and that Y drive lines assignment numbers to the Y diode arrays are identical to those given to the X diode arrays.
About the X and Y Core Drivers
The line selection scheme used for the X lines and the Y lines is a direct extension of the scheme illustrated in my July 1976 Byte Magazine article "Coincident Current Ferrite Core Memories," page 15, Figure 17, expanded as outlined in the Linear and Interface Circuits Data Book for Design Engineers by Texas Instruments, 1973, pages 10-32 thru 10-35 (Type SN75325 Memory Drivers Typical Application Data).
The line selection scheme used for the X lines and the Y lines is a direct extension of the scheme illustrated in my July 1976 Byte Magazine article "Coincident Current Ferrite Core Memories," page 15, Figure 17, expanded as outlined in the Linear and Interface Circuits Data Book for Design Engineers by Texas Instruments, 1973, pages 10-32 thru 10-35 (Type SN75325 Memory Drivers Typical Application Data).
To summarize Line selection operation for X (Y is identical):
- To address a word in 4K memory, only one of 64 X lines is to be selected.
- 6 bits of address is required to uniquely distinguish 64 lines
- In Core Driver Select circuit, 3 bits of address selects one of AX00 thru AX07 lines, and another 3 bits selects one of BX00 thru BX07.
- So there are 8 * 8 = 64 unique ways of pairing AX to BX outputs.
- On the A(X or Y) Drivers drawing, two drivers are shown (the 75325 is a dual driver package)
- Each driver can be a current source or sink (but opposite that of the B X end)
- From the Table, there are 8 A X drivers total
- Each A X Driver is driven from a unique select line AX00 thru AX07
- Each A X Driver is wired to an 8-connection diode array for 64 total connections
- So each of the eight A 8-connection diode arrays is selected (driven source) by a unique select line AX00 thru AX07
- Each of 64 A X core drive lines is wired to its own A X diode array connection of 64 possible
- On the B(X or Y) Drivers drawing, four drivers are shown
- Each driver can be sink or source (but opposite that of A X end)
- From the Table, there are 8 B X drivers total
- Each B X driver is driven from a unique select line BX00 thru BX07
- Each B X driver is wired to a 4-connection diode array for 32 total connections
- So each of the eight B 4-connection diode arrays is selected (driven sink) by a unique select line BX00 thru BX07
- A pair of 64 B X core drive lines is wired together to their own B X diode array connection of 32 possible
- To maintain unique core drive selection, none of the eight core drive lines connecting to a given B X diode array can have an A X diode array in common. (There are two separate diode arrays in each B (X or Y) TID133 package)
Walk-through example:
To drive current (holes, or maybe plusitrons ;-) ) thru core drive line X#5 from A to B:
- Make A X drivers source, and B X drivers sink: X READ must be low (and X WRITE must be high)
- AR 10-15 = 50 octal: In Core Drive Select, 10S asserts (low)AX00 and 10P asserts (low)BX05
- (low)AX00 and (low)X READ activates AX core driver 4S output pin 2 and thus diode array 4P, which includes a connection to core drive line 5 at pin 9.
- (low)BX05 and (low)X READ activates BX core driver 8P output pin 10 and thus diode array 8M, which includes the connection to core drive line 5 at pin 4, but no other lines of A X diode array 4P.
To drive the current thru the same drive line #5 from B to A:
- Make the A X drivers sink, and N X drivers source: X WRITE must be low (and X READ must be high)
- the same core drivers are selected by (low)AX00 and (low)BX05 as above, except the the sink/source output selection is reversed:
- (low)X WRITE activates AX core driver 4S output pin 7 (and 4P diode array as before)
- (low)X WRITE activates BX core driver 8P output pin 15 (and diode array 8M as before)
- To address a word in 4K memory, only one of 64 X lines is to be selected.
- 6 bits of address is required to uniquely distinguish 64 lines
- In Core Driver Select circuit, 3 bits of address selects one of AX00 thru AX07 lines, and another 3 bits selects one of BX00 thru BX07.
- So there are 8 * 8 = 64 unique ways of pairing AX to BX outputs.
- On the A(X or Y) Drivers drawing, two drivers are shown (the 75325 is a dual driver package)
- Each driver can be a current source or sink (but opposite that of the B X end)
- From the Table, there are 8 A X drivers total
- Each A X Driver is driven from a unique select line AX00 thru AX07
- Each A X Driver is wired to an 8-connection diode array for 64 total connections
- So each of the eight A 8-connection diode arrays is selected (driven source) by a unique select line AX00 thru AX07
- Each of 64 A X core drive lines is wired to its own A X diode array connection of 64 possible
- On the B(X or Y) Drivers drawing, four drivers are shown
- Each driver can be sink or source (but opposite that of A X end)
- From the Table, there are 8 B X drivers total
- Each B X driver is driven from a unique select line BX00 thru BX07
- Each B X driver is wired to a 4-connection diode array for 32 total connections
- So each of the eight B 4-connection diode arrays is selected (driven sink) by a unique select line BX00 thru BX07
- A pair of 64 B X core drive lines is wired together to their own B X diode array connection of 32 possible
- To maintain unique core drive selection, none of the eight core drive lines connecting to a given B X diode array can have an A X diode array in common. (There are two separate diode arrays in each B (X or Y) TID133 package)
Walk-through example:
To drive current (holes, or maybe plusitrons ;-) ) thru core drive line X#5 from A to B:
- Make A X drivers source, and B X drivers sink: X READ must be low (and X WRITE must be high)
- AR 10-15 = 50 octal: In Core Drive Select, 10S asserts (low)AX00 and 10P asserts (low)BX05
- (low)AX00 and (low)X READ activates AX core driver 4S output pin 2 and thus diode array 4P, which includes a connection to core drive line 5 at pin 9.
- (low)BX05 and (low)X READ activates BX core driver 8P output pin 10 and thus diode array 8M, which includes the connection to core drive line 5 at pin 4, but no other lines of A X diode array 4P.
To drive the current thru the same drive line #5 from B to A:
- Make the A X drivers sink, and N X drivers source: X WRITE must be low (and X READ must be high)
- the same core drivers are selected by (low)AX00 and (low)BX05 as above, except the the sink/source output selection is reversed:
- (low)X WRITE activates AX core driver 4S output pin 7 (and 4P diode array as before)
- (low)X WRITE activates BX core driver 8P output pin 15 (and diode array 8M as before)
X and Y Core Select Lines Connection to Drivers Error
After wiring all the X and Y select lines from the stack to the line drivers, I realized that I had wired all the stack X select lines to the Y drivers, and the Y select lines to the X drivers, and that the error was in the wire lists I had prepared. For a while I was really irked at this state of affairs, but eventually decided to leave the wiring in place since the stack select lines and and X-Y core driver logic was entirely symmetric with respect to X and Y. Besides, it wasn't like I would ever have to explain this confusion to anyone... (except for the matter of inhibit driver banks - see just below).
After wiring all the X and Y select lines from the stack to the line drivers, I realized that I had wired all the stack X select lines to the Y drivers, and the Y select lines to the X drivers, and that the error was in the wire lists I had prepared. For a while I was really irked at this state of affairs, but eventually decided to leave the wiring in place since the stack select lines and and X-Y core driver logic was entirely symmetric with respect to X and Y. Besides, it wasn't like I would ever have to explain this confusion to anyone... (except for the matter of inhibit driver banks - see just below).
Inhibit Drivers for the Stack
Inhibit lines
The core stack has 144 inhibit windings coming out to 4 connectors (J1 thru J4 on connector map above), or 8 windings for each of the 18 bit planes. I had been using the Select Line (Fig 12), Inhibit Line (Fig 13), and Sense Amplifier (Fig 14) test circuits of the Byte article to discover the core stack organization, but the inhibit winding layout proved to be too mysterious for this approach to be very efficient in sorting things out. I needed to find out how the windings were distributed in a bit plane and which ones served the 4K quadrant I was using, how the windings segments were mapped to core select line ranges, and the current direction in each winding needed to result in inhibit action.
Needing more functionality to proceed, I implemented the X-Y Driver logic and Sense Amplifiers as described on this page, and using the Read-Write control logic presented in Fig. 15a of the Byte article.
Inhibit lines
The core stack has 144 inhibit windings coming out to 4 connectors (J1 thru J4 on connector map above), or 8 windings for each of the 18 bit planes. I had been using the Select Line (Fig 12), Inhibit Line (Fig 13), and Sense Amplifier (Fig 14) test circuits of the Byte article to discover the core stack organization, but the inhibit winding layout proved to be too mysterious for this approach to be very efficient in sorting things out. I needed to find out how the windings were distributed in a bit plane and which ones served the 4K quadrant I was using, how the windings segments were mapped to core select line ranges, and the current direction in each winding needed to result in inhibit action.
Needing more functionality to proceed, I implemented the X-Y Driver logic and Sense Amplifiers as described on this page, and using the Read-Write control logic presented in Fig. 15a of the Byte article.
So I found out that all 8 inhibit lines pass through the bit planes within the quadrant I used: a
group of 4 lines rotated being inhibit for the first 32 X select lines
(X0 with i0, X1 with i1, X2 with i2, X3 with i3, X4 with i0, X5 with
i2,... X31 with i3), and similarly a second group of 4 lines rotated
being inhibit for the last 32 X select lines. So what was the stack design point in splitting up the inhibit line in a bit plane into 8 segments? I guessed it was probably to cut down on heat generation: about 400ma typical inhibit current through a (measured) 7.5 ohm winding segment generates 1.2 watts per segment: 9.6 watts for just 1 of the 16 bit planes (for about 50% of the time if the memory is continuously accessed). Not wanting to build and switch among eight inhibit driver banks, I compromised and connected adjacent pairs of inhibit winding groups in series (see the red connecting lines in the Inhibit Winding Connectors diagram, above right), and added three additional driver banks to four total to drive the four effective windings in each of the 16 bit planes.
The four inhibit driver banks are shown on the Inhibit Drivers Logic drawing, above center. The first is indicated by the IC locations 1U - 8U and 1V - 8V and diode arrays T2 and T6 (see Inhibit Driver Board Layout, above left); the remaining three by the included table, which shows the Location coordinate substitutions for the alpha and beta symbol markings in the drawing.
The Inhibit Drivers drawing does not show the subsequent modification to enable one of the four banks based on select line address ranges which map to the inhibit driver bank. The modification substitutes type 7437 NAND buffer (installed at 8T) outputs for the pullup resistor (and connection to +5volts) in each bank, to drive pins 1 and 7 of each driver in the bank. The bank is enabled (based on inputs INH0 - INH15, common to all banks) if its NAND buffer output is "high". Only one bank is enabled for a given write based on Y driver address information input to the NAND buffers. (Although Y address information is used for bank switching, the stack select lines being controlled by the addressing are the X lines, as noted in the subsection "X and Y Core Select Lines Connection to Drivers Error" above.)
The four inhibit driver banks are shown on the Inhibit Drivers Logic drawing, above center. The first is indicated by the IC locations 1U - 8U and 1V - 8V and diode arrays T2 and T6 (see Inhibit Driver Board Layout, above left); the remaining three by the included table, which shows the Location coordinate substitutions for the alpha and beta symbol markings in the drawing.
The Inhibit Drivers drawing does not show the subsequent modification to enable one of the four banks based on select line address ranges which map to the inhibit driver bank. The modification substitutes type 7437 NAND buffer (installed at 8T) outputs for the pullup resistor (and connection to +5volts) in each bank, to drive pins 1 and 7 of each driver in the bank. The bank is enabled (based on inputs INH0 - INH15, common to all banks) if its NAND buffer output is "high". Only one bank is enabled for a given write based on Y driver address information input to the NAND buffers. (Although Y address information is used for bank switching, the stack select lines being controlled by the addressing are the X lines, as noted in the subsection "X and Y Core Select Lines Connection to Drivers Error" above.)
36 Inhibit Control
The Inhibit Control logic consists of four ganged 74157 data-selectors/multiplexers which select the 16-bit source for presentation to the inhibit drivers during the memory write cycle. the high MDR->MEM signal selects the data held in the MDR for when the write data (MDRBIT0-15) comes from the CPU, or when low selects the data (MEMR0-15) held in the sense amplifiers read buffer from a just completed destructive read cycle for a write refresh of the read data. the (low) INH ENABLE allows the selected data to appear at the 74157 outputs (otherwise the outputs are all held low).
38 Sense Amplifier / Read Buffer Board
The Sense Amplifier / Read Buffer logic drawing does not have a separate
Board Layout, and is missing some component information. A closeup
photo of this 5" x 6" board is shown at the right. The two resistors
across each sense loop are 100 ohms 5% . The pullup resistor is 1K ohms.
The eight dual sense amplifier ICs are LM7524. The four quad-latch ICs
are 7475.
The sense amplifiers each connect to one of the sense lines of the sixteen
136 x 128 bit planes (128 x 128 used) in the 4K portion of the stack being used. The analog sense signal is fed to a differential amplifier and through a threshold detector, which converts the input voltage (either polarity) exceeding an adjustable threshold to TTL logic "1", and logic "0" otherwise. A single threshold adjustment is shared by both sense amplifiers in the dual package. On the board there are eight 200 ohm potentiometers for manually adjusting these thresholds (fortunately very seldom).
The purpose of the sense amplifier is to detect that one of the 16384 cores (which is at the intersection point of X and Y select lines for the word being read) "flipped" in its connected bit plane during the read portion of a memory read-write cycle, while ignoring read half-select noise from the other cores and the smaller blip from a selected core already in the "flipped" state. Stack and core manufacturing tolerances ensure that all cores in the stack produce flip signals strong enough and of long enough duration that that the outputs of all 16 amplifiers can be tested and strobed into buffer latches in parallel at the same time, as done in the logic by the (low) SENSE STROBE signal. (Of course the selection, inhibit, and sense electronics and environmental factors must be controlled to ensure the stack is operated within its tolerances.)
The purpose of the sense amplifier is to detect that one of the 16384 cores (which is at the intersection point of X and Y select lines for the word being read) "flipped" in its connected bit plane during the read portion of a memory read-write cycle, while ignoring read half-select noise from the other cores and the smaller blip from a selected core already in the "flipped" state. Stack and core manufacturing tolerances ensure that all cores in the stack produce flip signals strong enough and of long enough duration that that the outputs of all 16 amplifiers can be tested and strobed into buffer latches in parallel at the same time, as done in the logic by the (low) SENSE STROBE signal. (Of course the selection, inhibit, and sense electronics and environmental factors must be controlled to ensure the stack is operated within its tolerances.)
35 Read / Write Control Logic
I wrote the Byte article "Coincident Current Ferrite Core Memories" near the end of 1975 when the logic pieces described above were working together and the CPU (completed roughly a year earlier - with no peripherals other than keyboard) was able to execute instructions from the core memory.
However, the memory control logic was a hodge-podge of (intentionally) temporary circuitry, built on the circuit in Fig 15a of the Byte article. So I replaced this temporary logic with the Read / Write Control Logic shown here, retaining the X and Y and inhibit timing for the "read then write" cycle, and consolidating additional logic for initiating a memory read-write cycle and indicating its completion, and generating the (low) SENSE STROBE signal for capturing the sense amplifier read data. The input signal MCLK is a fixed 2MHz clock. Input MEM->MDR going high triggers a read (data to MDR) and write refresh cycle, the signal MDR->MEM going high triggers a read (data discarded) and write cycle - these signals are expected to remain high until the MEM DONE output signal goes high (it's low while the memory is in its read-write cycle: busy).
However, the memory control logic was a hodge-podge of (intentionally) temporary circuitry, built on the circuit in Fig 15a of the Byte article. So I replaced this temporary logic with the Read / Write Control Logic shown here, retaining the X and Y and inhibit timing for the "read then write" cycle, and consolidating additional logic for initiating a memory read-write cycle and indicating its completion, and generating the (low) SENSE STROBE signal for capturing the sense amplifier read data. The input signal MCLK is a fixed 2MHz clock. Input MEM->MDR going high triggers a read (data to MDR) and write refresh cycle, the signal MDR->MEM going high triggers a read (data discarded) and write cycle - these signals are expected to remain high until the MEM DONE output signal goes high (it's low while the memory is in its read-write cycle: busy).