Other-1 Computer with ferrite core memory
Jim R Jones

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Old stuff: OTHER-1 Minicomputer hobby project 1974-6

(NOTE: During 2006-7, I hosted a site from my home (via ISP Speakeasy) which described the Other-1, but I lost web hosting capability when I switched ISPs in 2008. This site, set up in October 2012, is hosted by "webs.com".)
The OTHER-1 is a homebrew 16-bit word minicomputer with core storage that I designed and built during 1974-1976. Its instruction set and I/O bus mechanism are similar to those of several commercial minicomputers I was familiar with at the time, including the PDP-8, Raytheon 703, and Data General 800 / 1220, with some added twists of my own. (The name "Other-1" is a reference to the last entry of the "Experience With Computers" list of systems then appearing on data processing job application forms.) It was built with simple construction, troubleshooting access, and reliable function in mind, so it is not particularly compact or fast. My goal was less about performance and efficiency, and more about core-based storage, fun with features, and implementing my own approach at low cost.
The OTHER-1 digital logic is almost entirely SSI 7400 series TTL (14 and 16 pins) along with some MSI items (74181 Arithmetic Logic Units, shift registers & counters, UART). The digital logic wiring was done with wire-wrap sockets mounted on two phenolic boards with a square grid of holes on .1" centers to accept the wire-wrap pins. About 230 ICs were used for the instruction control, registers, keyboard, and I/O bus logic. Most of these ICs were purchased on the surplus market, along with the wire-wrap sockets - generally the sockets were more expensive than the ICs plugged into them.

The board of processor registers (address, IC, instruction, accumulators, arithmetic logic, etc) was constructed first, followed by the board of instruction control logic. Each register or control function was incrementally added and statically tested. The cabinet mounting and front panels were prepared next; the mounting allows the logic wire-wrap boards to swing out so the ICs can be removed & inserted from the front. Then the final logic 5V power supply was built.

See the "Other-1 Board Layouts" album in the Photo Gallery for physical layouts of the Registers, Instruction Control Logic, X-Y Drivers, Inhibit Drivers, and Keyboard / TV Typewriter Interfaces boards.

Go to the CPU Logic page to see the CPU logic drawings, descriptions, and information about relating the drawings to their Board Layouts. The Photo Gallery also has the drawings in album "Core Memory Logic".

The control panel has the look and functionality of many minicomputers of the period, with switch-selectable display of the contents of the various registers, toggle switches for entry of machine instructions or execution start address, and single step, run, and reset push-buttons. The keyboard is a surplus item, providing ASCII character codes in parallel format and interfaced to the computer via the I/O bus.

The toggle switches were typically used to enter short test loops or utility programs to allow other programs to be loaded from or punched to paper tape. The keyboard was usable only when a loaded program was running to support it.
The OTHER-1 memory is implemented around a surplus RCA Spectra 70 3D core stack, made by Electronic Memories, Inc.,  with 64x68x4 (=17408) 18-bit words. With all its connectors and mounting rails, it is about 12.5" across x 6.5" front-to-back x 4.5" high.

The stack itself is about 4.5" x 4.5" x 2.5" high. There are 18 bit planes stacked in the 2.5" dimension. Each 4.5" x 4.5"  bit plane consists of a rectangular array of 128 x 136 cores, but is physically organized into 4 groups of 64 x 68 cores.

I built a Heathkit 15 MHZ dual trace scope kit so I could figure out enough of the core stack characteristics to get the memory running - what is the current needed to get cores to "flip" magnetization direction, and just how are the sense and inhibit lines wired with respect to the X-Y drive lines? Each of the four core groups on a bit plane has its own sense winding, but shares X and Y drive lines with other groups on the plane as well as with all other planes, and shares four inhibit windings with the other three groups on the plane. Inhibit current direction matters, so winding directions through the cores and mapping to stack connectors needed to be determined as well.

The core stack and its drive electronics were then added to the computer. Of the total core stack capacity I wired up about 1/4 with the electronics needed to get 4096 16-bit words actually used. It took about 140 ICs for the drive and sense electronics.  Of these, the array line select drivers and diode arrays were expensive and not available surplus - part of the reason only some of the stack was used.

The core stack driver electronics were built on two wirewrap boards mounted to swing out at the rear of the Other-1: inhibit drivers above, and X-Y selection drivers below. The stack is mounted below a horizontal shelf separating the computer logic boards from the core stack driver boards. The shelf holds a small wire-wrap board with the 16 sense amplifiers used for detecting the selected core stack word, and the CPU clock module.

I had plans to expand to 16384 words - I left room to double the X-Y drivers (extra space on the board to rear in fourth photo above), and would need three more sense-amp assemblies like the one shown in the photo immediately above. But it turned out there was plenty of room for the kind of programs I could write for this computer.
The Photo Gallery "Core Memory Logic" album contains the logic drawings for the Core X-Y Drivers Select, Inhibit Drivers and Control, Read / Write Control, and Sense Amplifiers. Refer to the Byte Core Memory Article (links below) for an overview of this logic. A more detailed description of the logic and interpretation of the logic drawings is provided on page Magnetic Core Memory Logic Details.
The Photo Gallery "OTHER-1 Views" album contains additional captioned photos of the computer and its memory.
BYTE Magazine Core Memory article and where to find it.
After I had gotten the OTHER-1 running with its core memory, I wrote an article about my experience of determining the characteristics of a surplus core stack, describing the needed off-the-shelf line driver and sense integrated circuitry and suggested timing, adjusting the sense amplifiers sensitivity, and determining the read strobe point timing. The article, "Coincident Current Ferrite Core Memories", was published in the July 1976 issue of BYTE Magazine.

NOTE: I still live in Colorado Springs, but a few blocks away at a different address than the one published in the article.
The full issue July 1976 Byte (Vol 00 Number 11) containing the Core Memory article, as well as many other Byte issues can be found at archive.org in pdf and e-reader formats.

Other locations the Core Memory article can be found :

Links to a scan & an OCR version of the original article as well as a pdf of the entire July 1976 Byte issue can be found can be found on Wouter's site  on page Wouter's Classic Computer Collection in the Wouter's Computer Bits section.

The actual OCR article version in a nice web-readable format with figures added is maintained on Ed Thelen's Nike Missile Web Site on the Documents, Links & Videos page in the Magnetic Core Memory section.

In 2006 I found out from co-workers that my article was on the web. My thanks to Wouter and Ed Thalen for digging out, preparing, and posting the article on their sites.

A list of links to homemade computers is kept on Andrew Holmse's site on page Links.
Instruction Set.
OTHER-1 Minicomputer instructions are all 16 bit (1 word) fixed length. There are 14 memory reference instructions, an I/O instruction, and four categories of an Operate instruction - Combine, Shift/Rotate, Test, and Miscellaneous. There are two 16 bit accumulator registers, A and B, that most of the instructions use. The accumulator registers share a single bit Link register for arithmetic operation results and shift/rotate operations.

Arithmetic is 16-bit twos-complement, and the Link register provides support for multi-word arithmetic.
See Instruction Set Details page for more information.
Computer Performance.
The memory was run at a fixed 2 MHz, and would do a read/write cycle in 8 usec whenever triggered. The cpu normally ran at 2 MHz, but could also be run at lower rates to aid hardware troubleshooting. The actual instruction times were some multiple of the clock cycle time, and varied by instruction type and addressing mode. With direct addressing, a JMP took 2 cycle periods, memory reference instructions with accumulator like TAD or LDA took 3 cycle periods, while a complex one like POP took up to 13 cycle periods. However, memory reference periods are stretched to to wait for the memory read-write cycle time, and the first period of all instructions is a fetch of the instruction from memory. So for example, the JMP actually took 8.5 usec, and the TAD took 16.5 usec.  (A low priority project to add a chunk of dram memory was never completed.) The instructions are all hard-wired SSI TTL.
After the OTHER-1 was built, I spent several years adding various peripherals - some for writing and saving programs, and others as experiments.

The OTHER-1 was "decommissioned" in about 1981, being replaced by a Heathkit H11 (LSI-11) microcomputer. Most of the peripherals and interfaces have been given away or re-purposed, but I have hung on to the OTHER-1 itself.

UPDATE: In June 2016, the OTHER-1 Computer was finally dismantled, and all wirewrap boards & ICs, memory stack, power supplies, and rack & panels were given away.